1. Field
The present invention relates generally to digital communications systems, and more specifically to a method and hardware architecture for parallel channel interleaving and de-interleaving.
2. Background
Digital communication systems use numerous techniques to increase the amount of information transferred while minimizing transmission errors. In these communication systems, the information is typically represented as a sequence of binary bits or blocks of bits called frames. The binary information is modulated to signal waveforms and transmitted over a communication channel. Communication channels tend to introduce noise and interference that corrupt the transmitted signal. At a receiver, the received information may be corrupted and is an estimate of the transmitted binary information. The number of bit errors or frame errors depends on the amount of noise and interference in the communication channel.
To counter the effects of transmission channel corruption, channel interleaving error correction coding is often used in digital communication systems to protect the digital information from noise and interference and reduce the number of bit/frame errors. Channel interleaving is employed in most modern wireless communications systems to protect against burst errors. A channel interleaver reshuffles encoded symbols in such a way that consecutive symbols are spread apart from each other as far as possible in order to break the temporal correlation between successive symbols involved in a burst of errors. A reverse de-interleaving operation is performed at the receiver side before feeding the symbols to a channel decoder. Typically, this interleaving, and subsequent de-interleaving are performed in an inefficient serial manner.
There is therefore a need in the art for a faster and more efficient parallel method of interleaving and de-interleaving having improved performance. Moreover, there is a need for the improved parallel interleaving and de-interleaving to have an easily implemented hardware architecture that can be constructed using basic logic gates with a short critical path delay.